1. Field of the Invention
This invention relates generally to computer peripheral devices, and in particular, to an apparatus and method for accessing a plurality of computer devices having common memory or input-output addresses on computer system buses operating at different speeds.
2. Description of the Related Technology
Computers, especially personal computers have gained substantial popularity among individual users at work or when working at home. Personal computers are now being utilized for jobs heretofore performed by mainframe computers and mini-computers. The rapidly growing popularity in the use of personal computers may, in part, be attributed to the substantial improvement in its speed of operation, ease of use, data storage capacity, and sophistication in displaying information to the computer user.
This has resulted in personal computers becoming more prevalent in the work place, and with more and more people depending on their livelihoods from the use thereof. Advances in computer technology have created the ability and thus the demand for higher resolution and faster updating of display information presented to the computer user. Typically, this information is displayed in a video form on a cathode ray tube (CRT).
Color is being used more often to display information and the number and resolution of the colors is constantly increasing with each advance in video display technology. The CRT video display requires a video graphics adapter (VGA) to convert the computer digital information into analog information for use by the CRT display. A VGA having high resolution and multiple colors, however, requires a great deal of digital information. This digital information may be transferred from the computer system memory over data and address buses the the VGA.
IBM compatible personal computers use an Industry Standard Architecture (ISA) bus for transferring digital data to and from peripheral devices such as the VGA. The ISA bus, though adequate for early black and white or video color graphics adapter (CGA) technology, does not have sufficient data throughput for quickly updating information to high resolution and color definition VGA systems. The ISA bus is slower than the computer system local bus which transfers information at data rates comparable to the host computer central processing unit (CPU).
In modern high speed computer systems using the more advanced video interface peripherals, the local bus is being used to connect the CPU to those peripherals which require high data throughput such as high resolution and color definition VGA systems. There is, however, a need for operating at least two VGA systems at the same time with the computer system. Examples of requirements for dual video displays are presentation transparency production, creating picture T-shirts, and presenting data simultaneously on both large and small CRT screens. Each video display may require its own VGA, and each VGA may be connected to different computer system bases such as, for example, local bus and ISA bus.
Each VGA which receives the same video data normally shares common CPU address locations, either input/output (I/O) or memory addresses. This is so because it would be inefficient and cumbersome to require the computer system and programs to duplicate data transfers of the same video information to completely different bus address locations.
What is needed is the ability to access I/O or memory address locations of two or more peripheral devices which share common addresses, even though on completely different computer system buses. These devices can be on different speed buses and have different operating times such as access selection and data transfer. Because of different access and data acceptance times between different computer system buses, for example, local and ISA buses, the access acceptance acknowledge signals must necessarily be different.
Various methods of reconciling different bus timing requirements have been attempted or theorized, however, all require some form of modification to existing bus standards and/or require implementation of additional electronic hardware logic to existing standard computer systems.
For example, a local bus device's acknowledge signal is disabled while the CPU processes the acknowledge signal from the other bus (ISA) device. If this is done, both the local bus device and the ISA device data transfers will be governed by the ISA device acknowledge signal only, however, data must be accepted by both devices. This creates a problem which arises if the ISA bus device is able to accept data more rapidly than the local bus device. After the ISA bus device accepts the data, it issues a ready signal to the CPU for more data. The CPU then sends more data on the next bus cycle.
Without additional hardware logic, the local bus device may fall behind the ISA bus device in accepting data since the CPU does not receive the local bus device ready signal because this signal is disabled. Even if an internal first-in first-out (FIFO) memory is used with the local bus device, data will eventually be lost because the local bus device has no way of holding up the CPU bus cycles.
A partial solution to this problem is for the local bus device to issue a CPU hold request. This hold request will force the CPU to release control of the bus upon completion of the current bus cycle, thereby, delaying the start of the next CPU bus cycle. This is only a partial solution because the CPU may be in bus lock when executing the bus cycles in question, thus, the CPU will not respond to the local bus device hold request.
Another possible solution would be to intercept the ready signal coming back from the ISA bus device. Intercepting the ISA bus device ready signal, however, would require re-synchronizing the timing of the bus devices because these devices must be in sync with the CPU bus cycle timing. Intercept of the ISA bus device ready signal would only work if the ISA device and CPU ready signals are isolated, but this requirement adds one additional CPU wait state into each ISA bus cycle. If the ready signals are not isolated, then intercept of the ISA ready signal will, in addition to adding one wait state, most likely prevent the CPU from properly reading data on the buses because the data may not be held valid long enough for proper CPU read operations.
A possible solution to not holding the CPU read operations long enough is to force a not ready on the ISA bus until the local bus device has completed the current command from the CPU. If the local bus returns a ready signal during the current bus cycle, its ready signal must be inhibited. Once the local bus device has finished accepting data, control logic on the ISA bus must either wait for the CPU bus cycle to finish before the ready signal is sent to the CPU, or generate a ready signal if the CPU bus cycle is finished so that the current CPU bus cycle may be terminated. This approach requires additional control logic and there are inherent synchronization problems between the two bus device ready signals. In addition, different logic circuits are required for each bus on which simultaneous data transfers are required.
What is needed is a way to write identical data simultaneously to different peripheral devices such as, for example, VGAs residing on different computer system buses and without losing data or requiring additional hardware logic implementations that make a computer system non-standard. It is important that different bus access speeds be accommodated without adding unnecessary bus cycles or special programming requirements.